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Verilog code to implement clock domain crossing, rate change asynchronous fifo depth calculation, half-adder, full-adder, tristate buffer, binary to gray conversion, $readmemh, file read write, $displ...
Verilog code for clock domain crossing, rate change fifo design or asynchronous fifo depth calculation, binary to gray conversion, file read write $display/$fdisplay, $readmemh functions, half-adder, full-adder, tri-state buffer and testbenches. Python scripts file read write, glob.glob module, hex to sign. Overflow, magnitude/integer conversion, sys.argv/commandline arguments, generate diamond pattern, stripoff white space, classes and global va...
Keywords: write, gain control, clock domain crossing, 4 bit adder, digital logic gates, full-adder, boolean functions, rate change fifo design, gray coding file read write, glob module
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